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19-3944; Rev 1; 5/06
KIT ATION EVALU E AILABL AV
2.2MHz, 2A Buck Converters with an Integrated High-Side Switch
Features
4.5V to 5.5V or 5.5V to 23V Input Voltage Range Output Voltage Adjustable Down to 0.6V 2A Output Current Synchronous Rectifier Driver Output (MAX5089) for Higher Efficiency Resistor-Programmable Switching Frequency from 200kHz to 2.2MHz External Synchronization and Enable (On/Off) Inputs Clock Output for Driving Second Converter 180 Out-Of-Phase (MAX5089) Integrated 150m High-Side n-Channel Power MOSFET Power-On Reset Output (MAX5088)/Power-Good Output (MAX5089) Short-Circuit Protection Thermal-Shutdown Protection Thermally Enhanced 16-Pin TQFN Package Dissipates 2.7W
General Description
The MAX5088/MAX5089 high-frequency, DC-DC converters with an integrated n-channel power MOSFET provide up to 2A of load current. The MAX5088 includes an internal power MOSFET to enable the design of a nonsynchronous buck topology power supply. The MAX5089 is for the design of a synchronous buck topology power supply. These devices operate from a 4.5V to 5.5V or 5.5V to 23V input voltage and a 200kHz to 2.2MHz resistor-programmable switching frequency. The voltage-mode architecture with a peak switch current-limit scheme provides stable operation up to a 2.2MHz switching frequency. The MAX5088 includes a clock output for driving a second DC-DC converter 180 out-of-phase and a power-on-reset (RESET) output. The MAX5089 includes a power-good output and a synchronous rectifier driver to drive an external low-side MOSFET in the buck converter configuration for high efficiency. The MAX5088/MAX5089 protect against overcurrent conditions by utilizing a peak current limit as well as overtemperature shutdown providing a very reliable and compact power source for point-of-load regulation applications. Additional features include synchronization, internal digital soft-start, and an enable input. The MAX5088/MAX5089 are available in a thermally enhanced, space-saving 16-pin TQFN (5mm x 5mm) package and operate over the -40C to +125C temperature range.
MAX5088/MAX5089
Ordering Information
PART MAX5088ATE+ MAX5089ATE+ TEMP RANGE -40C to +125C -40C to +125C PINPACKAGE 16 TQFN 16 TQFN PKG CODE T1655-2 T1655-2
Applications
xDSL Modem Power Supply Servers and Networks IP Phones/WLAN Access Points Automotive Radio Power Supply
+Denotes lead-free package.
Pin Configurations
PGND SGND 10 CKO 9
TOP VIEW
12
SOURCE
11
Selector Guide
PART MAX5088ATE CONFIGURATION Nonsynchronous Buck Synchronous Buck FEATURES RESET Output, Clock Output PGOOD Output, Synchronous FET Driver
SYNC 13 RESET 14 BST/VDD 15 EN 16
8 7
VL V+ BYPASS OSC
MAX5088
6 5
+ EP*
1 DRAIN 2 DRAIN 3 COMP 4 FB
MAX5089ATE
Pin Configurations continued at end of data sheet.
*EXPOSED PAD.
THIN QFN 5mm x 5mm
________________________________________________________________ Maxim Integrated Products
1
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2.2MHz, 2A Buck Converters with an Integrated High-Side Switch MAX5088/MAX5089
ABSOLUTE MAXIMUM RATINGS
V+ to PGND............................................................-0.3V to +25V BST/VDD, DRAIN to SGND ....................................-0.3V to +30V SGND to PGND .....................................................-0.3V to +0.3V BST/VDD to SOURCE...............................................-0.3V to +6V SOURCE to SGND..................................................-0.6V to +25V SOURCE or DRAIN Maximum Peak Current...............5A for 1ms VL to SGND ................-0.3V to the lower of +6V and (V+ + 0.3V) SYNC, EN, DL, CKO, OSC, COMP, FB to SGND...............................................-0.3V to (VL + 0.3V) BYPASS, CKO, OSC, COMP, FB, EN, SYNC, RESET, PGOOD Maximum Input Current .................................50mA *As per JEDEC51 Standard (multilayer board).
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RESET, PGOOD to SGND ........................................-0.3V to +6V BYPASS to SGND..................................................-0.3V to +2.2V VL and BYPASS Short-Circuit Duration to SGND ......Continuous Continuous Power Dissipation* (TA = +70C) 16-Pin TQFN (derate 33mW/C above +70C) ..........2666mW Package Thermal Resistance (junction to case) ............1.7C/W Operating Temperature Range .........................-40C to +125C Junction Temperature Range ............................-65C to +150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
ELECTRICAL CHARACTERISTICS
(V+ = VL = 5V or V+ = 5.5V to 23V, VEN = 5V, TA = TJ = -40C to +125C, unless otherwise noted. Circuits of Figures 5 and 6. Typical values are at TA = TJ = +25C.) (Note 1)
PARAMETER SYSTEM SPECIFICATIONS Input Voltage Range V+ Operating Supply Current V+ IQ 5.5 V+ = VL V+ = 12V, VFB = 0.8V ROSC = 10k, no switching V+ = 12V, VEN = 0V, PGOOD (MAX5089), RESET, CKO unconnected (MAX5088), ROSC = 10k Nonsynchronous (MAX5088), fSW = 1.25MHz, V+ = 12V, IOUT = 1.5A, VOUT = 3.3V Synchronous (MAX5089), fSW = 300kHz, V+ = 12V, IOUT = 1.5A, VOUT = 3.3V VL REGULATOR (VL)/BYPASS OUTPUT (BYPASS) VL Undervoltage Lockout VL Undervoltage Lockout Hysteresis VL Output Voltage BYPASS Output Voltage BYPASS Load Regulation VUVLO VHYST VL VBYPASS VBYPASS V+ = 5.5V to 23V, IVL = 0 to 40mA V+ = VL = 5.2V IBYPASS steps from 0 to 50A, V+ = VL = 5.2V 5.0 1.98 0 VL falling 4.1 137 5.2 2 1.2 5.5 2.02 10 4.3 V mV V V mV 4.5 1.8 23.0 5.5 2.5 V V mA SYMBOL CONDITIONS MIN TYP MAX UNITS
V+ Standby Supply Current
ISTBY
1
1.4
mA
79 % 90
Efficiency
2
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2.2MHz, 2A Buck Converters with an Integrated High-Side Switch
ELECTRICAL CHARACTERISTICS (continued)
(V+ = VL = 5V or V+ = 5.5V to 23V, VEN = 5V, TA = TJ = -40C to +125C, unless otherwise noted. Circuits of Figures 5 and 6. Typical values are at TA = TJ = +25C.) (Note 1)
PARAMETER SOFT-START Digital Soft-Start Period Soft-Start Steps ERROR AMPLIFIER (FB and COMP) FB to COMP Transconductance FB Input Bias Current FB Input Voltage Set Point COMP Sink-and-Source Current Capability INTERNAL MOSFETs On-Resistance n-Channel Power MOSFET Leakage Current Minimum Output Current Current Limit On-Resistance Internal Low-Side Switch On-Resistance nMOS On-Resistance pMOS Peak Sink Current Peak Source Current Clock Output-High Level Clock Output-Low Level Switching Frequency Minimum Controllable On-Time Maximum Duty Cycle RON ILEAK IOUT ILIMIT RONLSW ISWITCH = 50mA, V+ = VL = 5.2V V+ = VL = 5.2V, ISINK = 100mA VEN = 0V, VDRAIN = 23V, SOURCE = PGND VOUT = 3.3V, V+ = 12V (Note 2) 2.2 2 2.8 20 3.5 38 0.150 0.302 20 A A A gM IFB VFB ICOMP 0.5940 100 0.601 150 1.20 1.8 2.75 250 0.6095 mS nA V A Internal 6-bit DAC 4096 64 Clock periods Steps SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5088/MAX5089
SYNCHRONOUS RECTIFIER DRIVER (DL) (MAX5089 Only) RONDLN RONDLP IIDL_SINK IIDL_SOURCE VCKOH VCKOL fSW tON_MIN DMAX fSW = 2.2MHz MAX5088 MAX5089 82 82 VL = 5.2V, ISOURCE = 5mA VL = 5.2V, ISINK = 5mA ROSC = 5.62k V+ = VL = 5.2V ROSC = 41.2k ROSC = 10k 1900 275 1130 2100 312 1250 120 87.5 87.5 3.54 0.4 2400 350 1380 ns % kHz ISINK = 0.1A ISOURCE = 0.1A 1 1.9 1 0.75 6.7 11.1 A A V V
OSCILLATOR (OSC)/SYNCHRONIZATION (SYNC)/CLOCK OUTPUT (CKO) (MAX5088 Only)
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2.2MHz, 2A Buck Converters with an Integrated High-Side Switch MAX5088/MAX5089
ELECTRICAL CHARACTERISTICS (continued)
(V+ = VL = 5V or V+ = 5.5V to 23V, VEN = 5V, TA = TJ = -40C to +125C, unless otherwise noted. Circuits of Figures 5 and 6. Typical values are at TA = TJ = +25C.) (Note 1)
PARAMETER SYNC Frequency Range (Note 3) Sync Input to SOURCE RisingEdge Phase Delay (Note 4) Clock Output Phase Delay With Respect to SOURCE Waveform (Note 5) SYNC High Threshold SYNC Low Threshold Minimum SYNC High Pulse Width SYMBOL fSYNC SYNCPHASE ROSC = 10k, fSYNC = 1.2MHz ROSC = 10k, SYNC = GND (MAX5088 only) 2.0 0.8 100 CONDITIONS MIN 200 65 TYP MAX 2200 UNITS kHz degrees
CKOPHASE VSYNCH VSYNCL tSYNC_H
115
degrees V V ns
EN, RESET (MAX5088)/PGOOD (MAX5089) EN Threshold EN Input Bias Current RESET Threshold (Note 6) PGOOD Threshold (Note 6) FB to RESET or FB to PGOOD Propagation Delay RESET Active Timeout Period RESET, PGOOD Output Voltage RESET, PGOOD Output Leakage Current THERMAL SHUTDOWN Thermal Shutdown Thermal-Shutdown Hysteresis TSHDN Temperature rising +170 25 C C VIH VIL IEN VTH VTH tFD tRP VOL ILEAK ISINK = 3mA V+ = VL = 5.2V, VRESET or VPGOOD = 6V, VFB = 0.8V 140 VFB = VOUT VFB = VOUT 90 90 92.5 92.5 3 200 254 0.4 2 2.0 0.8 250 95 95 V nA % VOUT % VOUT s ms V A
Note 1: 100% tested at +125C. Limits over temperature are guaranteed by design. Note 2: Output current may be limited by the power dissipation of the package. See the Power Dissipation section in the Applications Information section. Note 3: SYNC input frequency is equal to the switching frequency. Note 4: From the SYNC rising edge to SOURCE rising edge. Note 5: From the rising edge of the SOURCE waveform to the rising edge of the CKO waveform. Note 6: RESET goes high 200ms after VOUT crosses this threshold, PGOOD goes high after VOUT crosses this threshold.
4
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2.2MHz, 2A Buck Converters with an Integrated High-Side Switch MAX5088/MAX5089
Typical Operating Characteristics
(V+ = VL = 5.2V, TA = +25C, Figures 5 and 6, unless otherwise noted.)
MAX5088 BUCK EFFICIENCY vs. OUTPUT CURRENT (VIN = 5V, fSW = 2.2MHz)
MAX5088/89 toc01
MAX5088 BUCK EFFICIENCY vs. OUTPUT CURRENT (VIN = 12V, fSW = 2.2MHz)
MAX5088/89 toc02
MAX5088 BUCK EFFICIENCY vs. OUTPUT CURRENT (VIN = 16V, fSW = 2.2MHz)
3.3V
MAX5088/89 toc03
90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 0 0 500 1000 1500 2000 3.3V 2.5V
80 3.3V 70 60 EFFICIENCY (%) 50 40 30 20 10 0 0 500 1000 1500 2000 2.5V
70 60 50 EFFICIENCY (%) 40 30 20 10 0
2500
2500
0
500
1000
1500
2000
2500
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
MAX5089 SYNCHRONOUS EFFICIENCY vs. OUTPUT CURRENT (VIN = 12V, fSW = 330kHz, L = 15H)
MAX5088/89 toc04
MAX5089 SYNCHRONOUS EFFICIENCY vs. OUTPUT CURRENT (VIN = 12V, fSW = 2.2MHz, L = 4.7H)
75 70 EFFICIENCY (%) 65 60 55 50 45 40 35 30 3.3V
MAX5088/89 toc05 MAX5088/89 toc07
95 90 85 EFFICIENCY (%) 80 75 70 65 60 55 50 0 500 1000 1500 2000 1.2V 2.5V 3.3V
80
2500
0
500
1000
1500
2000
2500
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
MAX5089 OUTPUT VOLTAGE vs. OUTPUT CURRENT (VIN = 12V, VOUT = 3.3V, fSW = 2.2MHz)
MAX5088/89 toc06
VL OUTPUT VOLTAGE vs. SWITCHING FREQUENCY
5.190 5.185 5.180 5.175 VL (V) VIN = 23V
3.315 3.310 OUTPUT VOLTAGE (V) 3.305 3.300 3.295 3.290 3.285 3.280 0 500 1000 1500 2000 OUTPUT CURRENT (mA)
5.170 5.165 5.160 5.155 5.150 100 600
VIN = 5.5V
1100
1600
2100
SWITCHING FREQUENCY (kHz)
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2.2MHz, 2A Buck Converters with an Integrated High-Side Switch MAX5088/MAX5089
Typical Operating Characteristics (continued)
(V+ = VL = 5.2V, TA = +25C, Figures 5 and 6, unless otherwise noted.)
MAX5089 VL DROPOUT VOLTAGE vs. SWITCHING FREQUENCY
MAX5088/89 toc08
SWITCHING FREQUENCY vs. ROSC
MAX5088/89 toc09
SWITCHING FREQUENCY vs. TEMPERATURE
2100 1850 FREQUENCY (kHz) 1600 1350 1100 850 600 350 ROSC = 40k ROSC = 20k ROSC = 10k ROSC = 6.04k
MAX5088/89 toc10
0.400 0.350 VL DROPOUT VOLTAGE (V) 0.300 0.250 0.200 0.150 0.100 0.050 0 100 600 1100 1600 2100 SWITCHING FREQUENCY (kHz) V+ = 5V V+ = 5.25V V+ = 5.5V
10,000
2350
FREQUENCY (kHz)
1000
100 0 10 20 30 40 50 60 70 RESISTANCE (k)
100 -40 10 60 110 TEMPERATURE (C)
MAX5089 LINE-TRANSIENT RESPONSE (IOUT = 1A, VIN STEP = 14V TO 21V)
MAX5088/89 toc11
MAX5089 LOAD-TRANSIENT RESPONSE (IOUT = 0.2A TO 1A)
MAX5088/89 toc12
VOUT = 3.3V VOUT
VIN = 12V VOUT = 3.3V 5V/div 100mV/div
VIN
0V VOUT 200mV/div IOUT 500mA/div 0A
100s/div
20s/div
MAX5089 LOAD-TRANSIENT RESPONSE (IOUT = 0.5A TO 2A)
VIN = 12V VOUT = 3.3V VOUT
MAX5089 SOFT-START AND SHUTDOWN (NO LOAD)
MAX5088/89 toc14
MAX5088/89 toc13
VIN = 12V 200mV/div VOUT 1V/div
0V IOUT 1A/div VEN 0A 5V/div 0V 1ms/div
20s/div
6
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2.2MHz, 2A Buck Converters with an Integrated High-Side Switch MAX5088/MAX5089
Typical Operating Characteristics (continued)
(V+ = VL = 5.2V, TA = +25C, Figures 5 and 6, unless otherwise noted.)
MAX5089 SOFT-START AND SHUTDOWN (IOUT = 2A)
MAX5088/89 toc15
VIN STARTUP WAVEFORM (EN CONNECTED TO VL)
MAX5088/89 toc16
RESET TIMEOUT
MAX5088/89 toc17
VIN = 12V
VEN 5V/div VOUT 2V/div
VIN
10V/div
VOUT
1V/div VPGOOD 5V/div
VEN VOUT
5V/div 2V/div
0V VEN 5V/div 0V 1ms/div
VRESET VIN 10V/div 1ms/div 40ms/div
5V/div
MAX5088 EXTERNALLY SYNCHRONIZED SWITCHING WAVEFORM
MAX5088/89 toc18
SHUTDOWN CURRENT vs. TEMPERATURE
5V/div 0V SHUTDOWN CURRENT (A) 450 5V/div 0V
MAX5088/89 toc19
500
VSYNC VCLKOUT
400
VSOURCE
10V/div 0V
350
VOUT 100ns/div
500mV/div 300 -40 10 60 TEMPERATURE (C) 110
SWITCHING SUPPLY CURRENT (ISW) vs. TEMPERATURE
MAX5088/89 toc20
CURRENT LIMIT vs. TEMPERATURE
2.70 2.65 CURRENT LIMIT (A) 2.60 2.55 2.50 2.45 2.40 2.35 VIN = 12V VOUT = 3.3V fSW = 1MHz
MAX5088/89 toc21
80 SWITCHING SUPPLY CURRENT (mA) 70 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 fSYNC = 600kHz fSYNC = 1.2MHz fSYNC = 2.2MHz MAX5088 VOUT = 3.3V IOUT = 1A
2.75
fSYNC = 300kHz 125
-40
10
60
110
TEMPERATURE (C)
TEMPERATURE (C)
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2.2MHz, 2A Buck Converters with an Integrated High-Side Switch MAX5088/MAX5089
Pin Description
PIN 1, 2 3 4 5 6 7 8 NAME DRAIN COMP FB OSC BYPASS V+ VL CKO 9 DL 10 11 12 13 SGND PGND SOURCE SYNC Low-Side Synchronous Rectifier Driver (MAX5089 Only). DL sources 0.7A and sinks 1A to quickly turn on and off the external synchronous rectifier MOSFET. Signal Ground Power Ground. Connect the rectifier diode's anode, the input capacitor negative terminal, the output capacitor negative terminal, and VL bypass capacitor negative terminal to PGND. Internal Power MOSFET Source Connection. Connect SOURCE to the switched side of the inductor as shown in Figure 5. External Synchronization Input. Connect SYNC to an external logic-level clock to synchronize the MAX5088/ MAX5089. Connect SYNC to SGND when not used. Open-Drain Active-Low Reset Output (MAX5088 Only). RESET remains low while the converter's output is below 92.5% of VOUT's nominal set point. When VOUT rises above 92.5% of its nominal set point, RESET goes high after the reset timeout period of 200ms (typ). Open-Drain Power-Good Output (MAX5089 Only). PGOOD remains low while the output is below 92.5% of its nominal set point. Internal MOSFET Driver Supply Input. Connect BST/VDD to an external ceramic capacitor and diode (see Figure 5). Enable Input. A logic-low turns off the converter. A logic-high turns on the device. Connect EN to VL for an always-on application. Exposed Pad. Connect to SGND. Solder EP to SGND to enhance thermal dissipation. FUNCTION Internal Power MOSFET Drain Connection. Use the MOSFET as a high-side switch and connect DRAIN to the input supply. Transconductance Error Amplifier Output. Connect a compensation network from COMP to SGND or from COMP to FB to SGND (see the Compensation section). Feedback Input. Connect a resistive divider from the output to FB to SGND to set the output voltage. Switching Frequency Set Input. Connect a resistor ROSC from OSC to SGND to set the switching frequency. When using external synchronization, program ROSC so that (0.2 x fSYNC) fSW (1.2 x fSYNC). ROSC is still required when external synchronization is used. Reference Bypass Connection. Bypass to SGND with a 0.22F or greater ceramic capacitor. Input Supply Voltage. V+ can range from 5.5V to 23V. Connect V+ and VL together for 4.5V to 5.5V input operation. Bypass V+ to SGND with a minimum of 0.1F ceramic capacitor. Internal Regulator Output. Bypass VL to SGND with a 4.7F ceramic capacitor and to PGND with a 0.1F ceramic capacitor. Connect V+ to VL for 4.5V to 5.5V operation. Clock Output (MAX5088 Only). CKO is an output with the same frequency as the converter's switching frequency and 115 out-of-phase. CKO is used to synchronize the MAX5088 to other MAX5088/MAX5089s.
RESET 14 PGOOD 15 16 -- BST/VDD EN EP
8
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2.2MHz, 2A Buck Converters with an Integrated High-Side Switch MAX5088/MAX5089
V+ DRAIN VL
LDO VL = 5.2V
SYNC RSENSE CKO OSC 4-PULSE SKIP 2V R 1V Q BYPASS 200m N2 BST/VDD OSCILLATOR
SOURCE Q ADAPTIVE BBM 30 fSW / 4 N3 PGND EN DIGITAL SOFT-START gm VREF = 0.6V FB COMP
VREF
SGND 200mV RESET
MAX5088
0.92 x VREF
N1 180ms DELAY
Figure 1. MAX5088 Block Diagram
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9
2.2MHz, 2A Buck Converters with an Integrated High-Side Switch MAX5088/MAX5089
V+ DRAIN LDO VL = 5.2V RSENSE OSCILLATOR OSC 4-PULSE SKIP 2V R 1V Q BYPASS 200m N2 BST/VDD VL
SYNC
SOURCE Q ADAPTIVE BBM VREF 30 fSW / 4 VL DL PGND EN DIGITAL SOFT-START gm VREF = 0.6V FB COMP N3
SGND 200mV PGOOD
MAX5089
0.92 x VREF
N1
Figure 2. MAX5089 Block Diagram
10
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2.2MHz, 2A Buck Converters with an Integrated High-Side Switch MAX5088/MAX5089
Detailed Description
PWM Controller
The MAX5088/MAX5089 use a pulse-width modulation (PWM) voltage-mode control scheme. The MAX5088 is a nonsynchronous converter and uses an external lowforward-drop Schottky diode for rectification. The MAX5089 is a synchronous converter and drives a lowside, low-gate-charge MOSFET for higher efficiency. The controller generates the clock signal from an internal oscillator or the SYNC input when driven by an external clock. An internal transconductance error amplifier produces an integrated error voltage at COMP, providing high DC accuracy. The voltage at COMP sets the duty cycle using a PWM comparator and an internal 1V P-P voltage ramp. At each rising edge of the clock, the converter's high-side n-channel MOSFET turns on and remains on until either the appropriate or maximum duty cycle is reached or the maximum current limit for the switch is detected.
MAX5089
The MAX5089 is intended for synchronous buck operation only. During the high-side MOSFET on-time, the inductor current ramps up. When the MOSFET turns off, the inductor reverses polarity and forward biases the Schottky rectifier in parallel with the low-side synchronous MOSFET. The SOURCE voltage is clamped to 0.5V below ground until the break-before-make time (tBBM) of 25ns is over. After tBBM, the synchronous rectifier MOSFET turns on. The inductor releases the stored energy as its current ramps down, and continues providing current to the output. The bootstrap capacitor is also recharged from the VL output when the MOSFET turns off. The synchronous rectifier keeps the circuit in continuous conduction mode operation even at light load. Under overload conditions, when the inductor current exceeds the peak current limit of the internal switch, the high-side MOSFET turns off and waits until the next clock cycle. The MAX5089, with the synchronous rectifier driver output (DL), has an adaptive break-before-make circuit to avoid cross conduction between the internal power MOSFET and the external synchronous rectifier MOSFET. When the synchronous rectifier MOSFET is turning off, the internal high-side power MOSFET is kept off until VDL falls below 0.97V. Similarly, DL does not go high until the internal power MOSFET gate voltage falls below 1.24V.
MAX5088
During each high-side MOSFET on-time (Figure 5), the inductor current ramps up. During the second half of the switching cycle, the high-side MOSFET turns off and forward biases the Schottky rectifier (D2 in Figure 5). During this time, the SOURCE voltage is clamped to 0.5V below ground. The inductor releases the stored energy as its current ramps down, and provides current to the output. During the MOSFET off-time, when the Schottky rectifier is conducting, the bootstrap capacitor (C10 in Figure 5) is recharged from the VL output. At light loads, the MAX5088 goes in to discontinuous conduction mode operation when the inductor current completely discharges before the next switching cycle commences. When the MAX5088 operates in discontinuous conduction, the bootstrap capacitor can become undercharged. To prevent this, an internal low-side 30 switch (see N3 in Figure 1) turns on, during the off-time, once every 4 clock cycles. This ensures that the negative terminal of the bootstrap capacitor is pulled to PGND often enough to allow it to fully charge to VL, ensuring the internal power switch properly turns on. The operation of the bootstrap capacitor wake-up switch causes a small increase in the output voltage ripple at light loads. Under overload conditions, when the inductor current exceeds the peak current limit of the internal switch, the high-side MOSFET turns off quickly and waits until the next clock cycle.
Input Voltage (V+)/Internal Linear Regulator (VL)
All internal control circuitry operates from an internally regulated nominal voltage of 5.2V (VL). At higher input voltages (V+) of 5.5V to 23V, VL is regulated to 5.2V. At 5.5V or below, the internal linear regulator operates in dropout mode, where VL follows V+. Depending on the load on VL, the dropout voltage can be high enough to reduce VL to below the undervoltage lockout (UVLO) threshold. For input voltages of lower than 5.5V, connect V+ and V L together. The load on V L is proportional to the switching frequency of the converter. See the VL Output Voltage vs. Switching Frequency graph in the Typical Operating Characteristics. For an input voltage higher than 5.5V, use the internal regulator. Bypass V+ to SGND with a low-ESR 0.1F or greater ceramic capacitor placed as close as possible to the MAX5088/MAX5089. Current spikes from VL disturb the internal circuitry powered by VL. Bypass VL with a lowESR 0.1F ceramic capacitor to PGND and a low-ESR 4.7F ceramic capacitor to SGND.
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11
2.2MHz, 2A Buck Converters with an Integrated High-Side Switch MAX5088/MAX5089
Enable
EN is an active-high input that turns the MAX5088/ MAX5089 on and off. EN is a TTL logic input with 2.0V and 0.8V logic-high and low levels, respectively. When EN is asserted high, the internal digital soft-start cycle slowly ramps up the internal reference and provides a soft-start at the output. This hysteresis provides immunity to the glitches during logic turn-on of the converter. Voltage variation at EN can interrupt the soft-start sequence and can cause a latch-up. Ensure that EN remains high for at least 5ms once it is asserted. Force EN low to turn off the internal power MOSFET and cause RESET to pull low (MAX5088) or cause PGOOD to pull low (MAX5089). Connect EN to VL when not used. the turn-on edge of the internal n-channel power MOSFET with a fixed propagation delay. When operating the MAX5088/MAX5089 with an external SYNC clock, ROSC must be installed. Program the internal switching frequency so that (0.2 x fSYNC) fSW (1.2 x fSYNC). The minimum pulse width for fSYNC is 100ns. Connect SYNC to SGND if synchronization is not used. The CKO output (MAX5088 only) is a logic-level clock with the same frequency as fSW and with 115 phase shift with respect to SYNC clock. Two MAX5088s can be connected in a master/slave configuration for twophase (180) interleaved operation. The CKO output of the master drives the SYNC input of the slave to form a dual-phase converter. To achieve the 180 out-of-phase operation, program the internal switching frequency of both converters close to each other by using the same ROSC value. When synchronizing the master-slave configuration using external clock, program the internal switching frequency using ROSC close to the external clock frequency (fSYNC) for 180 ripple phase operation (see Figure 7). Any difference in the internal switching frequency and fSYNC changes the phase delay. If both master and slave converters use the same power source, and share input bypass capacitors, the effective switching frequency at the input is twice the switching frequency of the individual converter. Higher ripple frequency at the input capacitor means a lower RMS ripple current into the capacitor.
Soft-Start/Soft-Stop
The MAX5088/MAX5089 include undervoltage lockout (UVLO) with hysteresis to prevent chattering during startup. The UVLO circuit holds the MAX5088/MAX5089 off until V+ reaches 4.5V and turns the devices off when V+ falls below 4.3V. The MAX5088/MAX5089 also offer a soft-start feature, which reduces surge currents and glitches on the input during turn-on. During turn-on when the UVLO threshold is reached or EN goes from low to high, the digital soft-start ramps up the reference (VBYPASS) in 64 steps. During a turn-off (by pulling EN or V+ low), the reference is reduced to zero slowly. The soft-start and soft-stop periods (tSS) are 4096 cycles of the internal oscillator. To calculate the soft-start/softstop period use the following equation: t SS = 4096 fSW
Current Limit
The MAX5088/MAX5089 protect against output overload and short-circuit conditions when operated in a buck configuration. An internal current-sensing stage develops a voltage proportional to the instantaneous switch current. When the switch current reaches 2.8A (typ) the power MOSFET turns off and remains off until the next on cycle. During a severe overload or short-circuit condition when the output voltage is pulled to ground the discharging slope of the inductor is VDS (the voltage across the synchronous FET), or VF (the voltage across the rectifying diode) divided by L. The short off-time does not allow the current to properly ramp down in the inductor, causing a dangerous current runaway and possibly destruction of the device. To prevent this, the MAX5088/ MAX5089 include a frequency foldback feature. When the current limit is detected the frequency is reduced to 1/4th of the programmed switching frequency. When the output voltage falls below 1/3rd of its nominal set point (VFB = 0.2V) the converter is turned off and soft-start cycle is initiated. This reduces the RMS current sourced by the converter during the fault condition.
fSW is the switching frequency of the converter.
Oscillator/Synchronization (SYNC)/Clock Output (CLKOUT)
The clock frequency (or switching frequency) is generated internally and is adjustable through an external resistor connected from OSC to SGND. The relationship between ROSC and fSW is: ROSC = 125 x 108 / s fSW
The adjustment range for f SW is from 200kHz to 2.2MHz. Connect a logic-level clock between 200kHz to 2.2MHz at SYNC to externally synchronize the MAX5088/ MAX5089's oscillator (see Figure 7). The MAX5088/ MAX5089 synchronize to the rising edge of the SYNC clock. The rising edge of the SYNC clock corresponds to
12
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2.2MHz, 2A Buck Converters with an Integrated High-Side Switch
At high input-to-output differential, and high switching frequency, the on-time drops to the order of 100ns. Even though the MAX5088/MAX5089 can control the on-time as low as 100ns, the internal current-limit circuit may not detect the overcurrent within this time. In that case, the output current during the fault may exceed the current limit specified in the Electrical Characteristics table. The MAX5088/MAX5089 may still be protected against the output short-circuit fault through the overtemperature shutdown. However, the output current may be as high as 5.5A. If the minimum on-time for a given frequency and duty cycle is less than 200ns, choose the inductor with a saturation current of greater than 5.5A. the device on again when the die temperature reduces by +25C. During thermal shutdown, the internal power MOSFET shuts off, DL pulls to SGND, VL shuts down, RESET (MAX5088)/PGOOD (MAX5089) pulls low, and soft-start resets.
MAX5088/MAX5089
Applications Information
Setting the Switching Frequency
The controller generates the switching frequency (fSW) through the internal oscillator or the signal at SYNC (f SYNC ), when driven by an external oscillator. The switching frequency is equal to fSW or fSYNC. A resistor, ROSC, from OSC to SGND sets the internal oscillator. The relationship between fSW and ROSC is: ROSC = 125 x 108 fSW
Power-on Reset (RESET) (MAX5088 Only)
RESET is an active-low open-drain output that pulls low when VOUT falls below 92.5% of its nominal set point. RESET goes high impedance when VOUT rises above 92.5% of its nominal set point, the soft-start period is complete, and the 200ms (typ) timeout period has elapsed. Connect a pullup resistor from RESET to a logic voltage or to VL. The internal open-drain MOSFET at RESET can sink 3mA while providing a TTL-compatible logic-low signal. Connect RESET to SGND or leave unconnected when not used.
Power-Good (PGOOD) (MAX5089 Only)
PGOOD is an open-drain, active-high output that pulls low when VOUT is below 92.5% of its nominal set point and goes high impedance when V OUT goes above 92.5% its nominal set point. Connect a pullup resistor from PGOOD to a logic voltage or to VL. PGOOD can sink up to 3mA while still providing a TTL-compatible logic-low output. Pulling EN low forces PGOOD low. Connect PGOOD to SGND or leave unconnected when not used.
where fSW is in Hertz, and ROSC is in ohms. For example, a 1.25MHz switching frequency is set with ROSC = 10k. Higher frequencies allow designs with lower inductor values and less output capacitance. Consequently, peak currents and I2R losses are lower at higher switching frequencies, but core losses, gatecharge currents, and switching losses increase. Rising clock edges on SYNC are interpreted as a synchronization input. If the SYNC signal is lost, the internal oscillator takes control of the switching rate, returning the switching frequency to that set by ROSC. This maintains output regulation even with intermittent SYNC signals. When using an external synchronization signal, set ROSC so that (0.2 x fSYNC) fSW (1.2 x fSYNC).
Buck Converter
Use the internal n-channel power MOSFET as a highside switch to configure the MAX5088/MAX5089 as a buck converter. In this configuration, SOURCE is connected to the inductor, DRAIN is connected to the input, and BST/VDD connects to the cathode of the bootstrap diode and capacitor. Figures 5 and 6 show the typical application circuits for MAX5088/MAX5089, respectively, in a buck configuration.
Thermal-Overload Protection
During a continuous output short-circuit or overload condition, the power dissipation in the MAX5088/ MAX5089 can exceed its limit. The MAX5088/MAX5089 provide an internal thermal shutdown to turn off the device when the die temperature reaches +170C. A thermal sensor monitors the die temperature and turns
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13
2.2MHz, 2A Buck Converters with an Integrated High-Side Switch MAX5088/MAX5089
Effective Input Voltage Range The MAX5088/MAX5089 can operate with input supplies ranging from 4.5V to 5.5V or 5.5V to 23V. The input voltage range (V+) can be constrained to a minimum by the duty-cycle limitations and to a maximum by the on-time limitation. The minimum input voltage is determined by: V + VDROP1 VIN _ MIN = OUT + VDROP2 - VDROP1 DMAX D MAX is the maximum duty cycle of 87.5% (typ). VDROP1 is the total drop in the inductor discharge path that includes the diode's forward voltage drop (or the drop across the synchronous rectifier MOSFET), and the drops across the series resistance of the inductor and PC board traces. VDROP2 is the total drop in the inductors charging path, which includes the drop across the internal power MOSFET, and the drops across the series resistance of the inductor and PC board traces. The maximum input voltage can be determined by: VOUT VIN _ MAX = t ON _ MIN x fSW where tON_MIN = 100ns and fSW is the switching frequency. Setting the Output Voltage For 0.6V or greater output voltages, connect a resistive divider from VOUT to FB to SGND. Select the FB to SGND resistor (R2) between 1k and 10k and calculate the resistor from OUT to FB (R1) by the following equation: V R1 = R2 x OUT - 1 VFB where VFB = 0.6V, see Figure 3. For designs that use a Type III compensation scheme, first calculate R1 for stability requirements (see the Compensation section) then choose R2 so that: R2 = See Figure 4. Inductor Selection Three key inductor parameters must be specified for operation with the MAX5088/MAX5089: inductance
14
value (L), peak inductor current (IPEAK), and inductor saturation current (ISAT). The minimum required inductance is a function of operating frequency, input-to-output voltage differential, and the peak-to-peak inductor current (IP-P). Higher IP-P allows for a lower inductor value, while a lower IP-P requires a higher inductor value. A lower inductor value minimizes size and cost, improves large-signal and transient response, but reduces efficiency due to higher peak currents and higher peak-to-peak output voltage ripple for the same output capacitor. On the other hand, higher inductance increases efficiency by reducing the ripple current. Resistive losses due to extra wire turns can exceed the benefit gained from lower ripple current levels especially when the inductance is increased without also allowing for larger inductor dimensions. A good compromise is to choose IP-P equal to 30% of the full load current. Use the following equation to calculate the inductance: V (V - V ) L = OUT IN OUT VIN x fSW x IP-P VIN and VOUT are typical values so that efficiency is optimum for typical conditions. The switching frequency is set by ROSC (see the Setting the Switching Frequency section). The peak-to-peak inductor current, which reflects the peak-to-peak output ripple, is worse at the maximum input voltage. See the Output Capacitor Selection section to verify that the worst-case output ripple is acceptable. The inductor saturation current is also important to avoid runaway current during continuous output short-circuit. At high input-to-output differential, and high switching frequency, the on-time drops to the order of 100ns. Though the MAX5088/MAX5089 can control the on-time as low as 100ns, the internal currentlimit circuit may not detect the overcurrent within this time. In that case, the output current during the fault may exceed the current limit specified in the EC table. The overtemperature shutdown protects the MAX5088/MAX5089 against the output short-circuit fault. However, the output current may reach 5.5A. Choose an inductor with a saturation current of greater than 5.5A when the minimum on-time for a given frequency and duty cycle is less than 200ns. Input Capacitors The discontinuous input current of the buck converter causes large input ripple current. The switching frequency, peak inductor current, and the allowable peak-topeak input voltage ripple dictate the input capacitance requirement. Increasing the switching frequency or the inductor value lowers the peak-to-average current ratio yielding a lower input capacitance requirement.
R1 x VFB VOUT - VFB
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2.2MHz, 2A Buck Converters with an Integrated High-Side Switch
The input ripple comprises mainly of VQ (caused by the capacitor discharge) and VESR (caused by the ESR of the input capacitor). The total voltage ripple is the sum of VQ and VESR. Assume the input voltage ripple from the ESR and the capacitor discharge is equal to 50% each. The following equations show the ESR and capacitor requirement for a target voltage ripple at the input: ESR = VESR IP-P IOUT + 2 VQ x fSW where: IP -P =
MAX5088/MAX5089
VIN x fSW x L VOUT _ RIPPLE VESR + VQ IP-P is the peak-to-peak inductor current as calculated above and fSW is the individual converter's switching frequency. The allowable deviation of the output voltage during fast transient loads also determines the output capacitance and its ESR. The output capacitor supplies the step load current until the controller responds with a greater duty cycle. The response time (tRESPONSE ) depends on the closed-loop bandwidth of the converter. The high switching frequency of MAX5088/ MAX5089 allows for a higher closed-loop bandwidth, thus reducing tRESPONSE and the output capacitance requirement. The resistive drop across the output capacitor's ESR and the capacitor discharge causes a voltage droop during a step load. Use a combination of low-ESR tantalum and ceramic capacitors for better transient load and ripple/noise performance. Keep the maximum output voltage deviation below the tolerable limits of the electronics being powered. When using a ceramic capacitor, assume an 80% and 20% contribution from the output capacitance discharge and the ESR drop, respectively. Use the following equations to calculate the required ESR and capacitance value: VESR ESROUT = ISTEP xt I COUT = STEP RESPONSE VQ where I STEP is the load step and t RESPONSE is the response time of the controller. The controller response time depends on the control-loop bandwidth.
(VIN - VOUT ) x VOUT
CIN = where IP-P =
IOUT x D(1- D)
(VIN - VOUT ) x VOUT
VIN x fSW x L
and
V D = OUT VIN where IOUT is the output current, D is the duty cycle, and f SW is the switching frequency. Use additional input capacitance at lower input voltages to avoid possible undershoot below the UVLO threshold during transient loading. Output Capacitors The allowable output voltage ripple and the maximum deviation of the output voltage during step load currents determine the output capacitance and its ESR. The output ripple comprises of VQ (caused by the capacitor discharge) and VESR (caused by the ESR of the output capacitor). Use low-ESR ceramic or aluminum electrolytic capacitors at the output. For aluminum electrolytic capacitors, the entire output ripple is contributed by VESR. Use the ESROUT equation to calculate the ESR requirement and choose the capacitor accordingly. If using ceramic capacitors, assume the contribution to the output ripple voltage from the ESR and the capacitor discharge to be equal. The following equations show the output capacitance and ESR requirement for a specified output voltage ripple. ESR = VESR IP-P IP-P COUT = 8 x VQ x fSW
Power Dissipation
The MAX5088/MAX5089 are available in thermally enhanced 16-pin, 5mm x 5mm TQFN packages that dissipate up to 2.7W at TA = +70C. When the die temperature reaches +170C, the MAX5088/MAX5089 shut down (see the Thermal-Overload Protection section). The power dissipated in the device is the sum of the power dissipated from supply current (PQ), power dissipated due to switching the internal power MOSFET (PSW), and the power dissipated due to the RMS cur-
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15
2.2MHz, 2A Buck Converters with an Integrated High-Side Switch MAX5088/MAX5089
rent through the internal power MOSFET (PMOSFET). The total power dissipated in the package must be limited so the junction temperature does not exceed its absolute maximum rating of +150C at maximum ambient temperature. Calculate the power lost in the MAX5088/MAX5089 using the following equations: The power dissipated in the switch is: PMOSFET = IRMS_MOSFET x RON where:
2 I xD IRMS _ MOSFET = (IOUT2 x D) + P-P 12
JC is the junction-to-case thermal resistance equal to 1.7C/W. TC is the temperature of the case and TJ is the junction temperature, or die temperature. The caseto-ambient thermal resistance is dependent on how well heat can be transferred from the PC board to the air. Solder the underside exposed pad to a large copper GND plane. If the die temperature reaches +170C the MAX5088/MAX5089 shut down and do not restart again until the die temperature cools by 25C.
Compensation
The MAX5088/MAX5089 have an internal transconductance error amplifier with an inverting input (FB) and output (COMP) available for external frequency compensation. The flexibility of external compensation and high switching frequencies for the MAX5088/MAX5089 allow a wide selection of output filtering components, especially the output capacitor. For cost-sensitive applications, use high-ESR aluminum electrolytic capacitors. For size sensitive applications, use low-ESR tantalum or ceramic capacitors at the output. Before designing the compensation components, first choose all the passive power components that meet the output ripple, component size, and component cost requirements. Secondly, choose the compensation components to achieve the desired closed-loop bandwidth and phase margin. Use a simple 1-zero, 2-pole pair (Type II) compensation if the output capacitor ESR zero frequency (f ZESR ) is below the unity-gain crossover frequency (fC). Use a 2-zero, 2-pole (Type III) compensation when the fZESR is higher than fC. Use procedure 1 to calculate the compensation network components when fZESR < fC. Procedure 1 (see Figure 3) Calculate the fZESR and fLC double pole: fZESR = fLC = 1 2 x ESR x COUT 1
IP-P is the peak-to-peak inductor current ripple. The power lost due to switching the internal power MOSFET is: PSW = VIN x IOUT x (tR + tF ) x fSW 4
tR and tF are the rise and fall times of the internal power MOSFET measured at SOURCE. The power lost due to the switching quiescent current of the device is: PQ = VIN x ISW (MAX5088) The switching quiescent current (I SW ) of the MAX5088/MAX5089 is dependent on switching frequency. See the Typical Operating Characteristics section for the value of ISW at a given frequency. In the case of the MAX5089, the switching current includes the synchronous rectifier MOSFET gate-drive current (ISW-DL). The ISW-DL depends on the total gate charge (Qg-DL) of the synchronous rectifier MOSFET and the switching frequency. (MAX5089) PQ = VIN x (ISW + ISW-DL) ISW-DL = Qg-DL x fSW where the Qg-DL is the total gate charge of the synchronous rectifier MOSFET at VGS = 5V. The total power dissipated in the device is: PTOTAL = PMOSFET + PSW + PQ Calculate the temperature rise of the die using the following equation: TJ = TC + (PTOTAL x JC)
2 x L x COUT
Calculate the unity-gain crossover frequency as: f fC = SW 20 If fZESR is lower than fC and close to fLC, use a Type II compensation network where RFCF provides a midband zero (fmid,zero) and RFCCF provides a high-frequency pole.
16
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2.2MHz, 2A Buck Converters with an Integrated High-Side Switch
Calculate the modulator gain (GM) at the crossover frequency. GM = VIN ESR V x x FB VOSC ESR+ (2 x fc x L) VOUT First, select the crossover frequency so that: f fC SW 20 Calculate the LC double-pole frequency, fLC: fLC = 1 2 x L x COUT 1 at 0.75 x fLC 2 x R F x C F
MAX5088/MAX5089
where VOSC is the 1VP-P ramp amplitude and VFB = 0.6V. The transconductance error amplifier gain at fC is: GE/A = gm x RF The total loop gain at fC should be equal to 1: GM = GE/A = 1
or
Place a zero fZ = where:
RF =
VOSC (ESR + 2 x fC x L)VOUT VFB x VIN x gm x ESR
CF =
1 2 x 0.75 x fLC x RF
Place a zero at or below the LC double pole: 1 CF = 2 x RF x fLC Place a high-frequency pole at fP = 0.5 x fSW. Therefore CCF is: CCF = 1 x RF x fSW
with RF 10k. Calculate CA for a target unity crossover frequency, fC: CA = 2 x fC x L x COUT x VOSC VIN x RF 1 ) at fZESR. 2 x R A x C A 1 2 x fZESR x C A
Place a pole ( fP1 =
RA =
Procedure 2 (see Figure 4) When using a low-ESR ceramic-type capacitor as the output capacitor, the ESR frequency is much higher than the targeted unity-gain crossover frequency (fC). In this case, Type III compensation is recommended. Type III compensation provides a low-frequency pole (DC) and two pole-zero pairs. The locations of the zero and poles should be such that the phase margin peaks at fC. fC fP = =5 The fZ fC is a good number to get approximately 60 of phase margin at fC. However, it is important to place the two zeros at or below the double pole to avoid conditional stability.
Place a second zero, fZ2, at 0.2 x fC or at fLC, whichever is lower. R1 = 1 - RA 2 x fZ2 x C A
Place a second pole (f P2 =
1 ) 2 x RF x CCF at 1/2 the switching frequency. CCF = CF (2 x 0.5 x fSW x RF x CF ) -1
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17
2.2MHz, 2A Buck Converters with an Integrated High-Side Switch MAX5088/MAX5089
VOUT
R1
gm R2 VREF RF CCF
COMP
CF
Figure 3. Type II Compensation Network
VOUT
CCF
RA CA
R1
RF
CF
R2 VREF
gm
COMP
Figure 4. Type III Compensation Network
18
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2.2MHz, 2A Buck Converters with an Integrated High-Side Switch
Improving Noise Immunity
When using the MAX5088/MAX5089 in noisy environments, adjust the controller's compensation to improve the system's noise immunity. In particular, high-frequency noise coupled into the feedback loop causes duty-cycle jitter. One solution is to lower the crossover frequency (see the Compensation section). 5) Keep the power traces and load connections short. This practice is essential for high efficiency. Use thick copper PC boards to enhance full-load efficiency and power dissipation capability. 6) Ensure that the feedback connection from FB to COUT is short and direct. 7) Route high-speed switching nodes (BST/VDD, SOURCE) away from the sensitive analog areas (BYPASS, COMP, FB, and OSC). Use internal PC board layers for SGND as EMI shields to keep radiated noise away from the IC, feedback dividers, and the analog bypass capacitors.
MAX5088/MAX5089
PC Board Layout Guidelines
Careful PC board layout is critical to achieve lowswitching power losses and clean stable operation. Use a multilayer board whenever possible for better noise immunity. Follow these guidelines for good PC board layout: 1) Solder the exposed pad to a large copper plane under the IC. To effectively use this copper area as a heat exchanger between the PC board and the ambient, expose this copper area on the top and bottom side of the PC board. Do not make a direct connection of the exposed pad copper plane to the SGND (Pin 10) underneath the IC. Connect this plane and SGND together at the return terminal of the V+ bypass capacitor 2) Isolate the power components and high-current paths from sensitive analog circuitry. 3) Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. 4) Connect SGND and PGND together close to the return terminals of the VL and V+ high-frequency bypass capacitors near the IC. Do not connect them together anywhere else.
Layout Procedure
1) Place the power components (inductor, CIN, and C OUT) first, with ground terminals close to each other. Make all these connections on the top layer with wide, copper-filled areas (2oz copper recommended). 2) Group the gate-drive components (boost diodes and capacitors, and VL bypass capacitor) together near the controller IC. 3) Make the ground connections as follows: a) Create a small-signal ground plane underneath the IC. b) Connect this plane to SGND and use this plane for the ground connection for BYPASS, COMP, FB, and OSC. c) Connect SGND and PGND together at the return terminal of V+ and VL bypass capacitors near the IC. Make this the only connection between SGND and PGND.
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19
MAX5088/MAX5089
2.2MHz, 2A Buck Converters with an Integrated High-Side Switch
Figure 5. MAX5088 Buck Configuration
VL VIN 1 DRAIN EN R9 10k RESET 14 PGOOD DRAIN 16 2 VOUT 3 COMP C2 10F JU1 VL R8 10k R3 750 1% C4 22pF C3 1200pF MAX5088 4 FB SYNC VL 7 V+ D1 C6 0.1F 11 PGND BST/VDD BYPASS C7 0.22F OSC R5 6.04k 1% SOURCE 8 VL 9 CKO SGND C8 0.1F 10 C9 4.7F 12 C10 0.1F VOUT L1 4.7H VOUT 15 R7 15 R10 10k 13 SYNC VIN R4 10k 1% C5 330pF SGND VL D2 C11 22F C12 0.1F PGND SGND PGND
20
VIN
+
PGND
C1 47F 35V
R1 27.4k 1%
______________________________________________________________________________________
R2 6.04k 1%
VL
VIN 1 DRAIN EN R9 10k 3 COMP PGOOD 14 PGOOD DRAIN 16 2 VOUT C2 10F JU1 VL
R8 10k
VIN
+
Figure 6. MAX5089 Buck Configuration
R3 750 1% C4 22pF C3 1200pF MAX5089 4 FB SYNC VL 7 V+ R10 10k D1 R7 15 C6 0.1F 11 PGND BST/VDD BYPASS C7 0.22F C10 0.1F VOUT OSC R5 6.04k 1% SOURCE 12 8 VL 9 DL R6 4.7 N1 3 4 PGND C8 0.1F 10 SGND C9 4.7F L1 4.7H VOUT 15 13 SYNC VIN R4 10k 1% C5 330pF SGND VL D2 1 256 C11 22F C12 0.1F PGND
PGND
C1 47F 35V
R1 27.4k 1%
R2 6.04k 1%
MAX5088/MAX5089
______________________________________________________________________________________
SGND
2.2MHz, 2A Buck Converters with an Integrated High-Side Switch
21
2.2MHz, 2A Buck Converters with an Integrated High-Side Switch MAX5088/MAX5089
VIN V+ DRAIN OUTPUT1 SOURCE CIN V+ DRAIN SOURCE OUTPUT2
DUTY CYCLE = 50% CLKIN SYNC CLKOUT MASTER SYNC SYNC SLAVE
CLKOUT (MASTER)
SOURCE (MASTER)
SYNCPHASE
SOURCE (SLAVE) CLKOUTPHASE
Figure 7. Synchronized Converters
Pin Configurations (continued)
PGND SGND
Chip Information
PROCESS: BiCMOS
TOP VIEW
SOURCE
12
11
10
DL 9
SYNC 13 PGOOD 14 BST/VDD 15 EN 16 EP*
8 7
VL V+ BYPASS OSC
MAX5089
6 5
+
1
2 DRAIN
3 COMP
4 FB
DRAIN *EXPOSED PAD.
THIN QFN 5mm x 5mm
22
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2.2MHz, 2A Buck Converters with an Integrated High-Side Switch
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX5088/MAX5089
______________________________________________________________________________________
QFN THIN.EPS
23
2.2MHz, 2A Buck Converters with an Integrated High-Side Switch MAX5088/MAX5089
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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